ASIC Design Lead-L2

Roles and Responsibilities

Hardware Design Lead - Responsible for the schematic entry, circuit design, circuit debugging, simulation, layout & verification of a complex chip block. Works on problems of complex scope, through extensive usage of standard concepts & principles. Works as a fully contributing team member, under broad guidance with independent planning & execution responsibilities. Requires extensive knowledge of at least one design area. Expected to continue to build upon domain knowledge and technical/ proprietary skills to reach levels of expertise, while adapting standard principles to new or changed conditions in day to day work. Has the ability to respond to detailed queries. Applies own judgment to independently determine a course of action, which is then executed independently post review. Responsible for coaching, guiding and mentoring junior members in the team to help them scale up faster

Skills and Job Requirements

Digital ASIC Design Concepts - L4 - Competent in basic digital design concepts, boolean arithmetic, decoding, interfacing, clocking, setup-hold timing concepts, One of Verilog/VHDL, One of NCSIM/Modelsim/VCS, CVS, DTS. Competent to go through the design document and understand the design. Setup-hold timing concepts, can perform unit level testing., Can perform standard cell circuit design, competent with spice [spectre, Hspice] simulators, understands LVS., Virtuoso, Calibre, Spectre. Competent to perform low level design involving control and data path designs Multi-clock design skills., Good documentation skills., can create a module level design document involving protocols amd can efficiently transform that to an HDL description; is lint-capable; is lec-capable., One of Verilog/VHDL, One of NCSIM/Modelsim/VCS, CVS, DTS, one of SpyGlass/Atrenta, one of Conformal LEC/ Formality. Expert in standard cell design, expert with spice simulators and LVS tools., Virtuoso, Calibre, Spectre. Competent to perform high level design can create a full IP level design document; is capable of reviewing design documents created by others; is capable of making power/area/speed trade-offs. Is capable of developing debug strategy for the design., One of Verilog/VHDL, One of NCSIM/Modelsim/VCS, CVS, DTS, one of SpyGlass/Atrenta, one of Conformal LEC/ Formality, Design Compiler, Power Compiler is capable of IP selection, bus fabric implementation, full chip integration, is aware of verification/DFT/PD friendly full chip implementation., Expert in complex IO design, has understanding of analog concepts, expert in circuit level verification with parasitic., Virtuoso, Calibre, Spectre, Assura. Competent to analyze the requirements and come-up with the overall architecture for the chip capable of performing HW-SW partitioning. Expert in optimal design partitioning and define the high level design. Is capable of IP selection., can create a full IP level design document, is capable of review